Semiconductor devices including metal features are difficult to scale down to smaller pitch sizes. As components of semiconductor devices continue to decrease in size, the metal features also need to be scaled down. The metal features in conventional semiconductor devices include a pattern of metal lines separated from one another by spaces. Each of the metal lines may have the same width and the metal lines may be equally spaced from one another, while other metal features may vary in size and spacing. Photolithography techniques, such as immersion photolithography, are used to form the metal features. Currently, 193 nm wavelength photolithography is limited to forming metal features at a pitch of about 80 nm. To improve the resolution of 193 nm wavelength photolithography, double patterning techniques (e.g., spacer assisted double patterning (SADP) have been used to reduce the pitch by up to one-half. Triple patterning techniques, quadruple patterning techniques (e.g., spacer assisted quadruple patterning (SAQP)), and octuplet patterning techniques have also been investigated to further scale down the pitch. While these patterning techniques may be used to form equally spaced patterns of metal lines, the patterning techniques are not effective to form metal features of variable sizes and having variable spacings between adjacent metal features. In addition, these patterning techniques are costly and require numerous process acts. Extreme ultraviolet (EUV) lithography has also been utilized to form metal features at a pitch of about 36 nm. However, the EUV lithography utilizes numerous and complex process acts and is expensive.